//: version "1.6"

module main;    //: root_module
supply0 w3;    //: /sn:0 {0}(274,298)(274,290)(258,290){1}
supply1 w1;    //: /sn:0 /dp:1 {0}(258,280)(273,280)(273,263){1}
supply0 w2;    //: /sn:0 {0}(265,178)(265,166)(243,166){1}
wire [7:0] w6;    //: /sn:0 {0}(168,91)(168,139)(203,139)(203,152){1}
wire [7:0] w0;    //: /sn:0 {0}(219,296)(219,331)(312,331)(312,139)(235,139)(235,152){1}
wire [7:0] w8;    //: /sn:0 {0}(219,255)(219,275){1}
wire [7:0] w10;    //: /sn:0 {0}(219,181)(219,239){1}
wire w5;    //: /sn:0 {0}(77,285)(182,285){1}
wire w9;    //: /sn:0 {0}(195,166)(185,166){1}
//: enddecls

  //: supply0 g4 (w3) @(274,304) /sn:0 /w:[ 0 ]
  //: supply1 g3 (w1) @(284,263) /sn:0 /w:[ 1 ]
  add g2 (.A(w6), .B(w0), .S(w10), .CI(w2), .CO(w9));   //: @(219,168) /sn:0 /w:[ 1 1 0 1 0 ]
  clock g1 (.Z(w5));   //: @(64,285) /sn:0 /w:[ 0 ] /omega:100 /phi:0 /duty:50
  //: dip g6 (w6) @(168,81) /sn:0 /w:[ 0 ] /st:0
  buf g7 (.I(w10), .Z(w8));   //: @(219,245) /sn:0 /R:3 /w:[ 1 0 ]
  //: supply0 g5 (w2) @(265,184) /sn:0 /w:[ 0 ]
  register g0 (.Q(w0), .D(w8), .EN(w3), .CLR(w1), .CK(w5));   //: @(219,285) /sn:0 /w:[ 0 1 1 0 1 ]

endmodule